The present invention relates to a semiconductor memory device and a manufacturing method thereof, and more particularly to a magnetic tunnel junction device using a magnetic tunnel junction layer and a fabricating method thereof.
As semiconductor memory technologies have been developed for highly integrated memory, a Magnetic Random Access Memory (MRAM) would become widely used among all types of memories because the MRAM has advantages on integration, operating speed, non-volatility. The MRAM includes a transistor configured to perform a switching function and a Magnetic Tunnel Junction (MTJ) device configured to store information. The MTJ device includes a magnetic tunnel junction layer and electrodes formed the top and bottom portions of the magnetic tunnel junction layer, wherein the magnetic tunnel junction layer includes two ferromagnetic layers and a tunnel barrier layer arranged therebetween. The magnetic tunnel junction layer has different Magneto-resistance (MR) depending on magnetization directions of the two ferromagnetic layers. Using the variation in voltage or current caused by the variation of the MR, it may be determined whether information stored in the MTJ indicates a logic level of “0” or “1”.
The MTJ device has a thin insulating layer between two magnetic layers. One of the magnetic layers, i.e., a free layer, has a free state where magnetization direction is easily changed when current flows. The other, i.e., a pinned layer, has magnetization direction set to a particular polarity. If the two magnetic layers have the same magnetization direction, resistance becomes low so that electrons can easily pass through them. This is a case that the stored data is recognized as a logic high level “1”. Otherwise, if the two magnetic layers have the opposite magnetization directions, resistance becomes high so that electrons hardly pass through them. This is a case that the stored data is recognized as a logic low level “0”.
In conventional MRAM, there may be a disadvantage in scalability because an additional digit line may be required to write data into the MTJ device. Further, magnetization process to a particular cell may affect to magnetization directions of nearby cells. Thus, it may be hard to manufacture products.
Spin-transfer torque (STT) technology makes MRAM modify above-mentioned features. A Spin-transfer torque Random Access Memory (STT-RAM) is so called as a Spin-transfer torque Magnetic Random Access Memory (STT-MRAM) in an advanced form of MRAM. At very small device scales, a spin-polarized current may transfer its spin angular momentum to a small magnetic element in the spin-transfer torque random access memory (STT-RAM). When a high density current passes through a ferromagnetic layer, if a magnetization direction of the ferromagnetic layer is different from spin-polarity of current, its magnetization direction may be forcibly adjusted to have the same polarity with electrons. Accordingly, if high density current flows from the pinned layer to the free layer, two layers have the same polarity. This is a case that the stored information is a logic high level “1”. Otherwise, when current flows from the free layer to the pinned layer, spin accumulation occurs at boundaries of a thin insulating layer so that two layers have the opposite polarities. This is a case that the stored information is a logic low level “0”.
As the STT technology applies to MRAM, write operation may be performed without the additional digit line, and interference between nearby cells may be alleviated. The STT-RAM has the advantages of lower power consumption and better scalability over conventional MRAM. The STT-RAM is non-volatile memory device such as a flash memory device because the magnetic direction or polarity remains in the STT-RAM even if power supply is cut off. In addition, the STT-RAM has a faster operating speed than the conventional SRAM or DRAM.
The STT-RAM includes the MTJ device configured to store information. The STT-RAM reads or writes the information based on magnetization directions or polarities of stacked layers in the MTJ device. However, if the MTJ device has a smaller size to increase operating speed and density of the STT-RAM, ferromagnetic layers included in the MTJ device have smaller area so as to have super paramagnetic characteristic. In this case, the MTJ device may not be used as an information storage element.
Further, as the conventional STT-RAM including the MTJ device of a stacked layer is scaled down, it may be difficult to control magnetization direction of the stacked layer so that it is more likely to malfunction. Thus, it may be hard to increase a chip yield to a desired level. As a result, there may be a limit to make the MTJ small because ferromagnetic layers may have a secured area to prevent an occurrence of malfunction.